Someone who admits he cannot write Verilog has just had an AI write him a handwritten-digit classifier that is heading for a real foundry. 2 The repository is there, the files are there, synthesis accepts the design. 1 What is still missing is the silicon proof.
Ken Chang calls the experience "very fun" and notes that he still does not know Verilog. 2 The anecdote alone would not earn an article. What makes it worth a closer look is the string of checks a "vibe-coded" circuit clears before hitting the frontier where an error stops being a bug in a file and becomes a physical object.
I reopened the repository and its commit history to understand what the AI actually produced, what passes through synthesis, and what remains constrained by the shuttle. 1
Co-written by an AI
The project's earliest trace says it clearly. The initial commit, dated 14 July 2026, carries the "Claude Fable 5" co-author line and a large pile of files: a PyTorch training pipeline, a weight generator, a 249-line Verilog file, a cocotb testbench, GitHub Actions for synthesis, and a .claude configuration. 1
In plain terms: the agent wrote the test code, the training, the circuit and a good part of the verification infrastructure. The human provides the objective, reviews, fixes blind spots, but does not write the chip's logic.
Weights burned into logic
The technical choice makes the project legible. The classifier is a small MLP, a three-layer network, fed by an MNIST image reduced to binarized 8×8 pixels. 1
The interesting part is how the network weights are stored. Instead of a RAM or ROM that would load coefficients at runtime, the weights are hard-wired into the netlist as ternary constants ({-1, 0, +1}). 1 At synthesis these constants fold into pure logic: no memory, no weight loading, no storage cell.
The computation is bit-serial. Each image is shifted in bit by bit, then runs in about twenty microseconds at 10 MHz — roughly 24 µs per digit for the most accurate variant. 1 The result appears on a 7-segment display and in binary.
The simulated proof
The project does not lean on a demo. It builds its case through systematic comparison. The repository contains a cocotb testbench that feeds 200 real MNIST images to the circuit and compares its output, bit for bit, with a reference integer model. 1 Every image must yield exactly the same classification as the fixed-point model.
The claimed accuracy figure, 80.3% over the 10,000-image test set, belongs to the exact integer model, not to the chip. 1 That is an important distinction to keep in mind: everything measured here is simulated and checked against the model, before fabrication.
That discipline is exactly what makes "vibe-coding" credible on such an unforgiving terrain. An AI can write Verilog that simulates; a simulation that systematically rejects even a single pixel of difference between the circuit and the model is a far more demanding form of proof than a simple "it seems to work".
Silicon does not forgive
Does physics still hold any ground against the AI? Yes, a lot.
The design targets a TinyTapeout shuttle. 3 It was first built on the IHP 130 nm process, then retargeted to the SKY 26c shuttle on the open-source SkyWater 130 nm process. 1 Area matters: the default variant occupies about 47% of a 2×2 tile. 1 You cannot place just anything in just any corner of the shuttle.
The date matters too. The SKY 26c shuttle closes submissions on 7 September 2026. 3 As I write, the design does not yet appear in the shuttle's official submitted-projects index. So, to be precise, it is on its way to the foundry, not yet etched. 3
The repository is tidy, the verification is serious, synthesis accepts the design. All of that counts, up to the fabricated chip. A bug that survives the whole simulation chain becomes, once the silicon is etched, an intermittent part that is hard to fix and expensive to re-spin. That is what software never sees.
What this shifts
This case does not prove that anyone can fabricate any chip without knowing anything about electronics. It shows something finer: someone who ignores HDL can, with an AI and serious verification, produce a design that clears the checks all the way to the foundry threshold.
The value is not AI magic. It is the verification discipline added to the process, something the "vibe-coded" software culture often neglects. On silicon, where there is no hot patch and no redeploy, that discipline stops being optional.
One question remains open, and it matches the subject's scale: how many of these "vibe-coded" designs will really survive the return of the chips? The AI writes the Verilog, verification turns it into proof, but only the shuttle decides whether a bug slipped through the net.